Rhine VT6107 PCI Fast Ethernet Controller

VT6107The VIA Rhine VT6107 Fast Ethernet controller is a cutting edge, feature-rich, single-ASIC solution for LAN-on-motherboard applications. By optimizing the throughput between the NIC and the PCI bus, the VT6107 drastically reduces CPU utilization and allows a transfer rate of up to 200 Mbps in full-duplex. The VT6107 supports advanced power management features for low power consumption, including Wake on LAN (WOL), and is implemented in a low power CMOS process.

Key Features

  • Pin- to -pin compatible with the VIA Networking Technologies Velocity VT6122 Gigabit Ethernet Controller.
  • Single-chip Fast Ethernet network interface controller (NIC) for PCI bus
    • PCI 2.2 specification compliant
    • 10/100 Mbps Ethernet communications
  • High Performance PCI Mastering Structure
    • On-chip bus master DMA
    • Transmit data buffer byte-alignment for low CPU utilization
    • Dynamic transmit packet auto-queuing for back-to-back transmission
    • Programmable activity polling intervals for description DMA
    • Programmable DMA arbitration priority to minimize overflow and underflow conditions
    • Supports PCI enhanced commands
  • Provides Standard 10Base-T/ 100Base-TX/ PHY Layer and Transceiver
    • Supports 10Base-T/100Base-TX with CAT5 UTP and STP
    • 10/100 Mbps N-way auto-negotiation
    • 10/100 Mbps full/half duplex operation
    • Supports MDI/MDIX auto-crossover
    • Automatic power saving for disconnected cables
    • Programmable LED outputs for link, activity, duplex, speed, and collision
  • Direct Programming EEPROM and Virtual EEPROM
    • Supports loading after power-up
    • Dynamic auto-reload
    • Dynamic direct programming for manufacturing
    • Supports loading from Virtual EEPROM
  • emBoot PXE Certification
  • Power management
    • Supports PCI Bus Power Management Interface Specification 1.0/1.1
    • Supports Advanced Configuration and Power Interface (ACPI) Specification 2.0
    • Supports Network Device Class Power Management Specification 1.0a
    • Wake-up event support link change / magic packets / unicast physical address / MS-defined pattern match
  • Flow Control
    • Supports IEEE 802.3X for full duplex
    • Multiple pause frame Xon/Xoff
  • Dual-power design: 3.3V I/O Power and 2.5V Core Power
  • 128-pin, 14 x 14 mm, EP-LQFP package
VIA Technologies, Inc.